Electronic musical instrument2009-10-12 00:00:00magnitude, and relative phase. The four coefficients required to control each of these partials are stored in the logical engine parameterstore, which is mapped into RAM arrays contained in the two PPCs by the interface chip (IFC) 42.
Wave generation is handled by stepping a pointer through a ROM containing a single quarter-cycle of a sine wave. This pointer is maintained automatically for each partial by PCC 32 which will hereafter be referred to as the Phase PCC. Itcontains RAM arrays which accomodate the 240 16-bit phase pointers and the 240 16-bit frequency control values. Each partial's phase pointer is incremented by the frequency control value once per sample cycle, and the resulting new pointer is handled tothe DPC for processing. A pointer is used to facilitate a table look up in the DPC as noted below. Thus, the larger the frequency constant, the fewer cycles required to step through the sine wave ROM and the higher the resultant frequency.
Amplitude envelope generation is handled by PCC #2, i.e. item 34, also referred to as the Amplitude PCC. The Amplitude PCC 34 contains RAM arrays for the 240 current amplitude values and the 240 attack/decay increments. Values for the currentamplitude of each partial are derived in a similar manner to that used for the phase pointers, and handed to the DPC for processing.
The DPC 36 takes in the phase and amplitude values, and performs the sine wave lookup and scaling functions on each partial. It also accumulates the final output sample, and provides stable data to the DAC 38 for conversion via its sample bus.
FIG. 2 shows a PCC chip in detail. Each PCC 32, 34 has as input the bidirectional engine data bus 44, the buffered host processor address bus 46 (see FIG. 1), and the interface control signals 48 (including interface handshaking and globalsynch) and address bus 48A. The master/slave
pin 45 allows the PCC to be tailored for the different jobs when master Phase PCC and when slave Amplitude PCC. Each contains two times 240 (i.e. 480) 16-bit words of RAM (58, 60) address multiplexing 54 anddecoding logic 56, a 16-bit adder 66, a programmable arithmetic clipper network 68 at the adder's output and control logic 62. They also contain a partial (sync address counter) section 52, used to maintain synchronization between both PCCs and the DPC.
When in the master mode the PCC functions as the wave generator by enabling the RAM 58 to contain the frequency data, and RAM 60 to contain the phase data. Correspondingly in the slave mode RAM 58 contains the attack/decay, and RAM 60 theamplitude information. The arithmetic clipper is allowed to wrap around when overflowing or underflowing during wave generation since wave generation is cyclical containing positive and negative values. However, during amplitude generation the clipper68 is constrained to stop at its maximum count (FFFF in hex notation) and at its minimum count (0000 in hex notation) The DPC 38 is responsible for taking in the phase and amplitude information generated for each partial by the PCCs, performing the sinewave lookup and scaling required, accumulating the final sixteen-bit sample, and presenting it to the DAC 38. It inputs the data from PCC 32 and PCC 34 bus and a SYNC signal from PCC 32 which synchronizes the engine 14, and produces a data resultcontaining all the audio information desired by the player. Due to the nature of the processing that it performs, it is a highly pipelined configuration.
Normally, the process of scaling a given partial value by an amplitude value requires a multiplication. However, due to the cost a...
